Pattern display signal generating apparatus and display apparatus using the same

ABSTRACT

A pattern display signal generating apparatus comprises a memory for storing predetermined pattern data and for outputting even-numbered bits and odd-numbered bits of the pattern data in parallel when scanned, a timing generator for generating an address for scanning the memory and for generating first and second clock signal having a predetermined phase difference, a first shift register for shifting the odd-numbered bits and outputting the same in series in synchronization with the first clock signal, a second shift register for shifting the even-numbered bits and outputting the same in series in synchronization with the second clock signal, and a logical operation circuit for performing at least one predetermined logical operation between outputs of the first and second shift registers to generate a pattern display signal.

This application is a continuation of application Ser. No. 169,903,filed Mar. 18, 1988, now abandoned.

BACKGROUND OF THE INVENTION

The present invention generally relates to a pattern display signalgenerating apparatus, and in particular to a pattern display signalgenerating apparatus capable of generating a pattern display signalwhich enables a pattern to be displayed so that a contour of thecharacter pattern is highlighted. The present invention further relatesto a pattern display apparatus using the present pattern display signalgenerating apparatus.

Conventionally, various display formats are used for producing a visualimage of patterns of characters figures on a picture plane, of a displayunit such as television sets. A highlighting display of characters isone example of the display formats. For example, when highlighting thedisplay of characters such as letters, numerals and symbols, the entirecharacter is highly and uniformly intensified, or only a contour of thecharacter is highly brightened. In the latter highlighting display, thecontour of the character is visually emphasized compared to otherportions thereof and is displayed.

A display apparatus comprises a pattern display signal generatingapparatus for generating a pattern display signal. The pattern displaysignal generating apparatus includes a character generator capable ofgenerating dot patterns of characters. One dot pattern is arranged in adot matrix of N lines and M columns. A dot pattern signal correspondingto one character is read cut from the character generator line by line,and is supplied as a pattern display signal to a signal processingcircuit. The signal processing circuit generates a video signal from thepattern display signal. The video signal is supplied to a display unitsuch as a cathode ray tube display unit, and the corresponding characteris displayed on a display picture plane thereof.

The conventional pattern display signal generating apparatus furtherincludes an operation circuit for generating a specific pattern displaysignal which enables the highlighting display of the contour of thecharacter (hereafter referred to as a contour highlighting displaysignal). The operation circuit generates the contour highlightingdisplay signal corresponding to a dot pattern of only the contour of thecharacter by using the dot pattern signal read out from the charactergenerator. In this case, the contour of the dot pattern has a width ofone dot in a direction of lines in the pattern (raster scan direction),for example.

The contour highlighting display signal for forming the contour patternhaving the width of one dot is generated by subjecting all the dots ofan N x M dot matrix to the following processing. Referring to FIG. 1which shows a portion of the N×M dot matrix, when a dot positioned atthe n'th line and the m'th column (hereafter represented as (n, m)) isprocessed, data, of its neighboring dots, i.e., 8 dots represented bythe shaded squares, are read out from the character generator inaddition to the datum of the dot at the position (n, m). The operationcircuit built into the pattern display signal generating apparatusperforms a predetermined operation on the 9 dot data, and decideswhether or not the dot at the position (n, m) is necessary to form thedot pattern of the contour. If the result of the operation isaffirmative, the dot subjected to the operation is decided to be a dotforming the contour.

However, the above-mentioned process for obtaining the dot pattern ofthe contour is very complex. In addition, the operation circuit which isdesigned specifically for implementing the aforementioned process cannotgenerate a different contour dot pattern having a width amounting to twodots in the direction of the line for example. From this reason, adegree of flexibility in the display format of the highlighting contouris poor.

In order to eliminate the above problems, a display pattern signalgenerating apparatus having a configuration shown in FIG. 2 is proposed.Referring to FIG. 2, a memory 10 stores dot pattern data of variouscharacters, and a memory 11 stores a dot pattern of a center or inner)region of each character obtained by removing a dot pattern of a contourthereof.

Data which is simultaneously read out from the memory 10 and 11 inresponse to the same address signal ADDS is subjected toparallel-to-serial conversion in shift registers 12 and 13,respectively. The conversion is performed in synchronization with aclock signal φ supplied to the shift registers 12 and 13. The shiftregisters 12 and 13 output serial signals to output terminals 14 and 15of the pattern display signal generating apparatus, respectively. At thesame time, the outputs of the shift registers 12 and 13 are supplied toan exclusive-OR circuit 16. A result of the exclusive-OR operation is acontour highlighting display signal related to the dot corresponding tothe address ADDS. The contour highlighting display signal is supplied toan output terminal 17. In this manner, the contour highlighting displaysignal related to all the N×M dots is generated.

However, the configuration shown in FIG. 2 must store two dot patternsassociated with one character, and thus a large memory capacity isnecessary.

SUMMARY OF THE INVENTION

Accordingly, a general object of the present invention is to provide anovel and useful pattern display signal generating apparatus in whichthe disadvantages of the above conventional apparatus have beeneffectively eliminated.

A more specific object of the present invention is to provide a patterndisplay signal generating apparatus of a simple configuration.

Another object of the present invention is to provide a pattern displaysignal generating apparatus which can provide a higher degree offlexibility in the design of the highlighting display.

Still another object of the present invention is to provide a patterndisplay signal generating apparatus capable of configuring a memory of asmaller capacity than the prior art for storing dot patterns ofcharacters.

The above objects of the present invention can be achieved by a patterndisplay signal generating apparatus comprising a memory for storingpredetermined pattern data and separately outputting even-numbered bitsand odd-numbered bits of the pattern data in parallel when scanned, atiming generator for generating an address for scanning the memory andfor generating first and second clock signals having a predeterminedphase difference, a first shift register for shifting the odd-numberedbits and outputting the same in series in synchronization with the firstclock signal, a second shift register for shifting the even-numberedbits and outputting the same in series in synchronization with thesecond clock signal, and a logical operation circuit for performing atleast one predetermined logical operation between outputs of the firstand second shift registers to generate a pattern display signal.

A further object of the present invention is to provide a patterndisplay apparatus using the above pattern display signal generatingapparatus.

The above object of the present invention is achieved by a patterndisplay apparatus comprising a control circuit (signal processing unit)for designating a character code corresponding to a character pattern tobe displayed, a pattern signal generating apparatus for generatingpattern display signals corresponding to a pattern to be displayed, asignal processing circuit for subjecting the pattern display signals topredetermined signal processing and for generating a corresponding videosignal, and a display unit for displaying a pattern corresponding to thevideo signal. The pattern generating signal generating apparatuscomprises a display memory for storing the character code from thecontrol circuit, a memory (character generator) for storingpredetermined pattern data and separately outputting even-numbered bitsand odd-numbered bits of the pattern data in parallel when a patterndata designated by the character code from the display memory isscanned, a timing generator for generating an address for scanning thememory and for generating first and second clock signals having apredetermined phase difference, a first shift register for shifting theodd-numbered bits and outputting the same in series in synchronizationwith the first clock signal, a second shift register for shifting theeven-numbered bits and outputting the same in series in synchronizationwith the second clock signal, and a logical operation circuit forperforming a plurality of predetermined logical operations betweenoutputs of the first and second shift registers to generate the patterndisplay signals to be supplied to the signal processing circuit.

Other objects, features and advantages of the present invention willbecome apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view for explaining an example of the conventional apparatusfor generating a display signal for displaying a highlighted contour ofa character;

FIG. 2 is a block diagram of an another example of the conventionalapparatus for generating a display signal for displaying highlightingcontour of a character;

FIG. 3 is a block diagram of a preferred embodiment of the presentinvention which is a part constituting a visual display apparatus;

FIG. 4A is a view for showing a part of a character dot pattern storedin a character generator shown in FIG. 3;

FIG. 4B through 4D are views for showing parts of character dot patternswhich can be generated by the configuration shown in FIG. 3; and

FIGS. 5(A) through 5(H) are views for explaining digital signals atdifferent parts in the configuration shown in FIG. 3.

PREFERRED EMBODIMENT OF THE INVENTION

Referring to FIG. 3, a reference numeral 100 denotes a preferredembodiment of the present invention. A central processing unit(hereafter simply referred to as a CPU) 50 provides a display memory 24with a character code corresponding to a character to be displayedthrough a terminal 25. A write address counter 20 generates a writeaddress for the display memory 24, and a read address counter 21generates a read address for the display memory 24. The write addressand the read address are supplied to a selector 22. A controller 23generates a read/write switching signal (hereafter simply referred to asR/W switching signal), and supplies the same to the selector 22 througha signal line 36. When the CPU 50 outputs the character code to thedisplay memory 24, the controller 23 provides the selector 22 with theR/W switching signal having a signal state which designates theselection of the write address generated by the write address counter20. At this time, the display memory 24 is maintained in a write modewhich is designated by a read/write signal which is generated by thecontroller 23 and passes through a signal line 37.

The display memory 24 is used to temporarily store character codes, eachof which indicates a corresponding character. When reading out thedesired character code from the display memory 24, it is kept in a readmode designated by the read/write signal from the controller 23. Thecharacter code in the display memory 24 is read out therefrom and issupplied to a character generator 26. At this time, the controller 23generates the R/W switching signal having a state which designates theselection of the read address generated by the read address counter 21.

The character generator 26 is a memory in which composite character dotpatterns, each corresponding to respective character codes which arestored. Each of the composite character patterns is composed of 32(lines) x 24 (columns) dots, for example. A composite character dotpattern is a specific dot pattern as shown in FIG. 4A. In this figure,lines following the sixth line are omitted for simplicity. A dotrepresented by "○" denotes a binary zero, and a dot represented by " "denotes a binary one.

Character dot patterns stored in the character generator 26 aredifferent from those stored in the conventional character generators.FIG. 4C shows a part of a character dot pattern which is normally storedin the conventional character generators and corresponds to thecharacter which is the same as the character related to the specificcharacter dot pattern shown in FIG. 4A. FIG. 4B shows a part of a dotpattern obtained by eliminating a dot pattern which forms a contour ofthe character dot pattern shown in FIG. 4C. That is, the dot patternshown in FIG. 4B is the dot pattern of a center or inner portion of thecharacter inside the contour. The dot pattern which forms the contour ofthe character dot pattern shown in FIG. 4B is shown in FIG. 4D. Thispattern is hereafter referred to as a contour dot pattern. Variouscontour dot patterns can be formed without difficulties by arbitrarilyextracting dots from the dot pattern shown in FIG. 4C.

A character dot pattern as shown in FIG. 4A can be obtained from itscontour dot pattern, for example. By way of example, the compositecharacter dot pattern shown in FIG. 4A can be obtained by using thecontour dot pattern shown in FIG. 4D in the following manner. As will bedescribed in detail later, the contour dot pattern shown in FIG. 4D isgenerated by performing the exclusive-OR operation between two adjacentdots in each line shown in FIG. 4A. For example, in the first linesshown in FIGS. 4A and 4D, the exclusive-OR operation is performedbetween the dots positioned at the sixth and seventh columns in thecomposite character dot pattern of FIG. 4A, and as a result of theoperation, a value is decided for the dot at the seventh column in thecontour dot pattern of FIG. 4D. Therefore, values of the dots at theseventh column in the composite character dot pattern of FIG. 4A can beobtained by use of the value of the dot at the sixth column in the dotpattern of FIG. 4A and the value of the dot at the seventh column in thedot pattern shown in FIG. 4D. Since the dot in the sixth column in FIG.4A has a value of 0, and the dot in the seventh column in FIG. 4D has avalue of 1, a value of the dot at the seventh column in FIG. 4A isdecided to be 1. This step for generating the dot data of the compositecharacter dot pattern from the contour dot pattern is carried outstarting with the dot positioned at the first column for each line.

For example, when deciding values of the dots in the first line of FIG.4A, the dot at the first column of FIG. 4D is initially processed. Avalue of the dot at the first column in FIG. 4D is a value of the dot atthe first column in FIG. 4A as it is. Next, the dot at the second columnin FIG. 4D is processed. Since the dot at the second column has a valueof 0, a value of the dot at the second column is decided to be 0. Inthis manner, values of the dots at-up to the sixth column in FIG. 4A aredecided to be 0. Thereafter, when the dot at the seventh column in FIG.4D is processed, the value of the sixth column in FIG. 4A which hasalready been obtained is referred to in addition to the value of the dotat the seventh column in FIG. 4D. Since the dot at the sixth column inFIG. 4A has a value of 0. and the dot at the seventh column in FIG. 4Dhas a value of 1, a value of the dot at the seventh column in FIG. 4A isdecided to be 1. Subsequently, the dot at the eighth column in FIG. 4Dis processed. Since both the dot at the seventh column in FIG. 4A andthe dot at the eighth column in FIG. 4D have a value of 1 , a value ofthe dot the eighth column in FIG. 4A is decided to be 0. In the abovemanner, the composite character dot pattern of FIG. 4A can be obtainedby using the contour dot pattern of FIG. 4D.

The above process may be summarized as follows. Firstly, consecutiveblack dot data in each line of the contour dot pattern shown in FIG. 4Dare represented by an arrangment of consecutive dot data in thecorresponding line of the composite character dot pattern shown in FIG.4A, in which black dot data are arranged for every other dot. Secondly,consecutive white dot data inside the contour dot pattern arerepresented by an arrangment of consecutive black dot data in thecorresponding line of the composite character dot pattern shown in FIG.4A. Thirdly, a change from a white dot datum to a black dot datum ineach line is represented as it is in the corresponding line of thecomposite character dot pattern shown in FIG. 4A. White dot data outsidethe contour dot pattern are represented as they are.

Returning to FIG. 3, a timing generator 27 supplies the charactergenerator 26 with a raster address signal for designating the 32 linesin sequence through an address line 38. Thereby, data of the dots in thedesignated line of the composite character dot pattern corresponding tothe character code are successively read out from the charactergenerator 26 in a parallel form line by line. At this time,even-numbered bits are read out in parallel on a bus line 41, andodd-numbered bits are read out in parallel on a bus line 42.

FIG. 5A shows a part of data which is simultaneously read out from thecharacter generator 26 in which the even-numbered bits and theodd-numbered bits are arranged on the same axis in sequence forsimplicity of the figure. The even-numbered bits and the odd-numberedbits are supplied to shift registers 29 and 28 through the bus lines 42and 41, respectively. As shown in FIGS. 5(D) and 5(E), the shiftregisters 28 and 29 are provided with clock signals φ₁ and φ₂ having aphase difference of, 180° which are generated by the timing generator 27and pass through signal lines 39 and 40 respectively. The shift register28 shifts each of the odd-numbered bits in parallel by respectivepredetermined times in synchronization with the clock signal φ₁, asshown in FIG. 5(C). In FIG. 5(C), a horizontal direction representstime. Then, the odd-numbered bits are output per one bit in seriesstarting with the smallest odd-numbered, bit (#1, in the illustratedexample). Each of the output bits has a pulse width twice that of theoriginal pulse width. Likewise, the shift register 29 shifts each of theeven-numbered bits in parallel by respective predetermined times insynchronization with the clock signal φ₂, as shown in FIG. 5(B). Then,the even-numbered bits are output per one bit in series starting withthe smallest even-numbered bit (#0, in the illustrated example). Each ofoutput bits has a pulse width twice that of the original pulse width.

As shown in FIGS. 5(B) and 5(C), adjacent even-numbered and odd-numberedbits shown in FIG. 5(A) overlaps with each other on a time axis. Theserial data from the shift registers 28 and 29 are supplied to an ANDcircuit 30, an OR circuit 31 and an exclusive OR circuit 32. Outputsignals of the AND circuit 30, OR circuit 31 and exclusive-OR circuit 32shown in FIGS. 5(F) through 5(H) are supplied to output terminals 33, 34and 35, respectively. The output signal of the AND circuit 30 is apattern display signal for displaying the pattern shown in FIG. 4B,which is the same as the pattern stored in the memory 11 shown in FIG.2. The output signal of the OR circuit 31 is a pattern display signalfor displaying the pattern shown in FIG. 4C, which is the same as thepattern stored in the memory 10 shown in FIG. 2. The output signal ofthe exclusive-OR circuit 32 is a contour highlighting display signal fordisplaying the pattern shown in FIG. 4D, which is the same as the signalat the terminal 17 shown in FIG. 2. It will be appreciated that thethree different pattern display signals obtained by the presentembodiment are generated from one pattern stored in the charactergenerator 26. On the other hand, the conventional apparatus utilizes thetwo character generators each having the same memory capacity as thatfor the present embodiment. As a result, according to the embodiment,the memory capacity is half that for the conventional apparatus. Inaddition to the above advantage, different contour highlighting displaysignals can be easily obtained by varying the composite character dotpatterns stored in the character generator 26. These results in animproved degree in the flexibility of the design of the displaypatterns.

The output signals from the AND circuit 30, OR circuit 31 andexclusive-OR circuit 32 are supplied to a conventional signal processingcircuit 60, respectively. The signal processing circuit 60 generates avideo signal from the above-mentioned output signals. At this time, theluminance of the video signal may be controlled by the above-mentionedoutput signals. For example, the luminance of the video signalcorresponding to the contour of the character is emphasized, compared tothat for the inner portion thereof. The video signal is supplied to acathode ray tube 70, so that the character is displayed on its pictureplane in a state where the brightness of the contour is highlighted.

The present invention is not limited to the above embodiment, butvarious variations and modifications may he made without departing fromthe scope of the present invention.

What is claimed is:
 1. A pattern display signal generating apparatuscomprising:a first bus line for odd-numbered bits; a second bus line foreven-numbered bits; memory means for storing predetermined pattern dataand for separately outputting even-numbered bits, to said second busline, and odd-numbered bits, to said first bus line, of the pattern datain parallel when scanned; timing generating means for generating anaddress for scanning the memory means and for generating first andsecond clock signals having a predetermined phase difference; firstshift register means for shifting the odd-numbered bits on said firstbus line for outputting the same in series in synchronization with thefirst clock signal; second shift register means for shifting theeven-numbered bits on said second bus line and for outputting the samein series in synchronization with the second clock signal wherein atiming with which the first shift register outputs the odd-numbered bitsoverlaps a timing at which the second shift register outputs theeven-numbered bits; and logical operation means for performing at leastone predetermined logical operation between outputs of the first andsecond shift register means to generate a pattern display signal.
 2. Apattern display signal generating apparatus as claimed in claim 1,wherein the first and second clock signals have a phase difference of180°, and therein the logical operation means performs the predeterminedlogical operation between adjacent even-numbered and odd-numbered bitswhich overlaps with each other on a time axis.
 3. A pattern displaysignal generating apparatus as claimed in claim 1, wherein thepredetermined pattern data is data generated from data related to acontour portion of a corresponding pattern, and the predeterminedpattern data has (a) a first bit arrangement in which consecutive blackdot data, of binary ones in each line of the contour pattern data, arerepresented in said predetermined pattern data by consecutive dot datahaving black dot data for every other dot, and (b) a second bitarrangement in which an area inside the contour portion is representedin said predetermined pattern data by consecutive black dot data, and(c) a third bit arrangement in which a change from a white dot datum toa block dot datum in said contour portion is represented as it is insaid predetermined pattern data.
 4. A pattern display signal generatingapparatus as claimed in claim 1, wherein the logical operation means isan exclusive-OR circuit, and an output of the exclusive-OR circuit formsa contour pattern display signal which is used for highlighting adisplay of a contour of a pattern.
 5. A pattern display signalgenerating apparatus as claimed in claim 1, wherein the logicaloperation means is an AND circuit, and an output signal of the ANDcircuit forms a display signal for displaying an inner portion of apattern excluding a contour portion thereof.
 6. A pattern display signalgenerating apparatus as claimed in claim 1, wherein the logicaloperation means is an OR circuit, and an output signal of the OR circuitforms a display signal for displaying the whole pattern.
 7. A patterndisplay signal generating apparatus as claimed in claim 1, wherein thepattern display signal generating apparatus further comprises displaymemory means for supplying a character code to the memory means as anaddress signal, a read/write address supply means for supplying read andwrite addresses for the display memory means, and an address selectingmeans for selecting one of the read and write addresses from theread/write address supply means.
 8. A pattern display apparatuscomprising:control means for designating a character code correspondingto a character pattern to be displayed; pattern signal generating meansfor generating pattern display signals corresponding to a pattern to bedisplayed; signal processing means for subjecting the pattern displaysignals to predetermined signal processing and for generating acorresponding video signal; and display means for displaying a patterncorresponding to the video signal, the pattern generating signalgenerating means comprising:a first bus line for odd-numbered bits, asecond bus line for even-numbered bits, a display memory means forstoring the character code from the control means, memory means forstoring predetermined pattern data and for separately outputtingeven-numbered bits, to said second bus line, and odd-numbered bits, tosaid first bus line, of the pattern data in parallel when a pattern datadesignated by the character code form the display memory means isscanned, timing generating means for generating an address for scanningthe memory means and for generating first and second clock signalshaving a predetermined phase difference, first shift register means forshifting the odd-numbered bits on said first bus line and for outputtingthe same in series in synchronization with the first clock signal,second shift register means for shifting the even-numbered bits on saidsecond bus line and for outputting the same in series in synchronizationwith the second clock signal wherein a timing with which the first shiftregister outputs the odd-numbered bits overlaps a timing at which thesecond shift register outputs the even-numbered bits, and logicaloperation means for performing a plurality of predetermined logicaloperations between outputs of the first and second shift register meansto generate the pattern display signals to be supplied to the signalprocessing means.
 9. A pattern display apparatus as claimed in claim 8,wherein the logical operation means is composed of an AND circuit, an ORcircuit, and an exclusive-OR circuit.
 10. A pattern display apparatus asclaimed in claim 9, wherein the first and second clock signals have aphase difference of 180°, and therein the logical operation meansperforms the predetermined logical operations between adjacenteven-numbered and odd-numbered bits which overlaps with each other on atime axis.
 11. A pattern display apparatus as claimed in claim 10,wherein the predetermined pattern data is data generated from datarelated to a contour portion of a corresponding pattern and wherein thepredetermined pattern data has (a) a first bit arrangement in whichconsecutive black dot data, of binary ones in each line of the contourpattern data, are represented in said predetermined pattern data byconsecutive dot data having black dot data for every other dot, and (b)a second bit arrangement in which an area inside the contour portion isrepresented in said predetermined pattern data by consecutive black dotdata, and (c) a third bit arrangement in which a change from a white dotdatum to a black dot datum in said contour portion is represented as itis in said predetermined pattern data, and wherein an output signal ofthe exclusive-OR circuit forms a display signal of a contour portion ofthe character pattern, and wherein the signal processing means processesthe video signal so that by use of the pattern display signal of thecontour portion, the contour portion is highlighted on a picture planeof the display means.